CV

My research builds compiler-centered hardware-software co-design systems for domain-specific computing, and more recently innovative agents that advance kernel development on new chips. The central problem is how real software demands can be translated into reusable architectural capabilities, realized as high-quality hardware, and exposed back to software through compiler interfaces and agentic workflows that remain analyzable, verifiable, and reusable.

Architecture customization. I explored compiler techniques and formal methods, especially e-graphs, to automate ISA customization and compiler adaptation. ISAMORE (DOI) finds reusable custom instructions by anti-unifying equivalent program fragments. Cayman (DOI) discovers accelerator opportunities from whole applications while optimizing control flow and data access. APS (DOI, GitHub) and Aquas (preprint) connect customized hardware capabilities to retargetable compiler support.

Hardware synthesis. I created intermediate representations at multiple abstraction levels and proposed synthesis passes that optimize timing, microarchitecture, mapping, and scheduling. Hector (DOI, GitHub) provides a multi-level MLIR substrate for hardware synthesis. Cement (DOI) and Cement2 (preprint) make cycle timing and temporal transactions first-class FPGA design abstractions. Clay (DOI) synthesizes microarchitecture-aware ASIP instructions, while SkyEgg (preprint) uses e-graphs for joint implementation selection and scheduling.

LLM techniques. I explored both LLMs for compilers and compiler/system techniques for LLMs, including innovative agents for accelerating kernel development on new chips. EggMind (preprint) uses LLMs to synthesize reusable equality-saturation strategies. IntelliC (GitHub) studies inspectable compiler representations for human and agent collaboration. Spine studies verification-bounded agentic co-design, using typed semantic boundaries and executable checks to connect design intent, architecture descriptions, hardware/compiler artifacts, and validation feedback in a traceable closed loop. PTO Runtime (GitHub) executes compiled task graphs for serving on Ascend chips and LingQu SuperPods. Hive (preprint) extends the systems view to multi-agent inference infrastructure.

The closed loop is that architecture customization exposes reusable hardware capabilities, hardware synthesis turns them into efficient implementations, and LLM-era techniques advance the earlier compiler and co-design toolchains while providing evolving capabilities that make the loop practical and self-improving.