CV

My research follows a compiler-driven approach to agile hardware-software co-design. Three coupled threads form a closed loop: architecture description and exploration discovers and formalizes reusable hardware capabilities; chip DSL and compilation express those capabilities and lower them into implementations; compiler optimization and LLM systems improve the resulting compiler, execution, and co-design workflows.

Current kernel model and agent work. At ByteDance Seed, I create an extensible benchmark of kernel programming and optimization tasks for dataflow-architecture chips, develop a layered knowledge and skill system across multiple compilation paths, and build full-spectrum data collection and training workflows for continual model evolution. The ultimate goal is a methodology and workflow that enable models and agents to rapidly acquire expert-level kernel optimization capabilities for new chip architectures.

Architecture description and exploration. I combine compiler analysis, formal methods, and architecture DSLs to represent and search design spaces while connecting customized hardware capabilities to programmable software. ISAMORE (DOI) discovers reusable custom instructions by anti-unifying equivalent program fragments; Cayman (DOI) identifies accelerator opportunities in complete applications while co-optimizing control flow and data access; APS (DOI, GitHub) and Aquas (ICCAD 2026) describe customized architectures through DSLs and expose them through complete hardware/software compiler stacks.

Chip DSL and compilation. I create DSLs and intermediate representations at multiple abstraction levels, then develop compilation and synthesis passes that optimize timing, microarchitecture, implementation selection, mapping, and scheduling. Hector (DOI, GitHub) provides multi-level MLIR foundations; Cement (DOI) and Cement2 (preprint) introduce cycle-deterministic DSL and temporal-transaction abstractions; Clay (DOI) makes ASIP instructions microarchitecture-aware; SkyEgg (preprint) jointly optimizes implementation selection and scheduling with e-graphs.

Compiler optimization and LLM systems. I explore LLMs for compiler and hardware-software co-design workflows, together with compiler and system support for LLM workloads. EggMind (preprint) synthesizes equality-saturation strategies; IntelliC (GitHub) studies inspectable representations for human-model compilation; Spine (GitHub) organizes verification-bounded cross-layer co-synthesis; PTO Runtime (GitHub) supports dynamic kernel fusion and distributed execution of compiled task graphs on Ascend chips and LingQu SuperPods; Hive (preprint) provides multi-agent inference infrastructure.