CV

Curriculum Vitae

General Information

Full Name Youwei Xiao (肖有为)
Email shallwe@pku.edu.cn
Phone +86 185 1920 4005

Education

  • 2022 - Present

    Beijing, China

    Ph.D. Candidate in Integrated Circuit Science and Engineering
    School of Integrated Circuits, Peking University
    • Advisor: Prof. Yun Liang
    • Research: agents for LLM infrastructure on emerging AI chips, grounded in compiler-driven hardware-software co-design
  • 2018 - 2022

    Beijing, China

    Bachelor of Science in Computer Science
    School of EECS, Peking University

Work Experience

  • 2026 - Present

    Beijing, China

    Large Language Model Algorithm Intern
    ByteDance Seed
    • Contributed to native multi-agent coding systems, focusing on orchestration strategies and workflow customization with programmable concurrency and human-in-the-loop workflows.
    • Applied these approaches to LLM infrastructure by evolving an abstraction-layered operator-optimization skill system and an agent-native compiler stack for emerging AI chips.
    • Curated agent development data and trajectories from real systems tasks, turning infrastructure work into training signals for stronger coding and systems agents.

Research

Agentic LLM infrastructure. My current research centers on agents for LLM infrastructure on emerging AI chips. I evolve an abstraction-layered operator-optimization skill system and an agent-native compiler stack, connecting operator implementation, chip-architecture-aware performance optimization, and toolchain auto-development; the resulting work improves LLM serving efficiency and turns real development trajectories into training data for stronger coding and systems agents.

Native multi-agent coding systems. I contribute to multi-agent orchestration strategies and workflow customization for long-horizon systems development, using programmable concurrency and human-in-the-loop workflows.

Compiler and runtime substrates. Earlier systems work provides the surfaces that agents can operate on. IntelliC (GitHub) studies inspectable compiler representations for human-agent collaboration. PTO Runtime (GitHub) executes compiled task graphs for serving on Ascend chips and LingQu SuperPods. Hive (preprint) exposes multi-agent LLM workloads to inference infrastructure, while Spine (GitHub) studies bounded agentic co-design across design intent, architecture, compiler, hardware, and execution evidence.

Compiler-driven agile chip design. My earlier research treats compilers as the organizing layer for architecture customization and hardware-software co-design. Hector (DOI, GitHub) provides multi-level IRs for hardware synthesis; Cement (DOI) couples the cycle-deterministic CmtHDL DSL with the CmtC timing-analysis and control-synthesis compiler; APS (DOI, GitHub) builds an open-source MLIR stack from architecture DSLs to hardware synthesis and software compilation, and Aquas (ICCAD 2026) extends it with domain-specific memory/synthesis directives and an e-graph retargetable compiler. Clay (DOI), Cayman (DOI), and SkyEgg (preprint) automate microarchitecture and accelerator optimization, while ISAMORE (DOI) and EggMind (preprint) structure compiler search with formal and LLM-guided methods.

Current direction: agents for LLM infrastructure on emerging AI chips Native multi-agent architecture Programmable concurrent model Human-in-the-loop workflows Orchestration and workflow customization Agentic LLM infrastructure Layered operator-optimization skills Agent-native compiler stack Chip-aware performance optimization LLM serving efficiency Make emerging AI chips serve LLM workloads more efficiently. Development trajectories Turn real systems work into data for stronger coding/systems agents. apply to improve service record trajectories train stronger agents Compiler-driven agile chip design foundations Represent intent -> optimize implementations -> execute and observe structured artifacts optimization methods execution feedback DSLs & compiler stacks DSLs and multi-level IRs expose hardware/software intent; compiler passes lower it to executable designs. Hector , Cement APS , Aquas Architecture & synthesis optimization Formal, e-graph, and compiler search automate ISA, microarchitecture, and accelerator optimization. ISAMORE , Clay , Cayman SkyEgg , EggMind Execution & co-design systems Inspectable artifacts, task graphs, and runtime feedback connect design intent to deployed systems. IntelliC , PTO Runtime Hive , Spine

Selected Publications

  • 2026
    LLM-Guided Strategy Synthesis for Scalable Equality Saturation
    arXiv preprint
    • Chenyun Yin*, Youwei Xiao*, Yuze Luo, Yuyang Zou, Yun Liang (*Equal contribution)
  • 2026
    Hive: A Multi-Agent Infrastructure for Algorithm- and Task-Level Scaling
    arXiv preprint
    • Zizhang Luo, Yuhao Luo, Youwei Xiao, Yansong Xu, Runlin Guo, Yun Liang
  • 2026
    ISAMORE: Finding Reusable Instructions via E-Graph Anti-Unification
    ASPLOS 2026 (Best Paper Award, 5/1048)
    • Youwei Xiao, Chenyun Yin, Yitian Sun, Yun Liang
  • 2025
    APS: Open-Source Hardware-Software Co-Design Framework for Agile Processor Specialization
    ICCAD 2025 (Invited Paper)
    • Youwei Xiao, Yuyang Zou, Yansong Xu, et al.
  • 2025
    Clay: High-level ASIP Framework for Flexible Microarchitecture-Aware Instruction Customization
    ICCAD 2025
    • Weijie Peng*, Youwei Xiao*, Yuyang Zou, et al. (*Equal contribution)
  • 2025
    Cayman: Custom Accelerator Generation with Control Flow and Data Access Optimization
    DAC 2025
    • Youwei Xiao, Fan Cui, Zizhang Luo, Weijie Peng, Yun Liang
  • 2024
    Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis
    FPGA 2024
    • Youwei Xiao, Zizhang Luo, Kexing Zhou, Yun Liang
  • 2022
    HECTOR: A Multi-Level Intermediate Representation for Hardware Synthesis Methodologies
    ICCAD 2022
    • Ruifan Xu, Youwei Xiao, Jin Luo, Yun Liang

Honors and Awards

  • 2026
    学术之芯
    2026年度，北京大学集成电路学院；授予8人
  • 2026-2027
    博士研究生校长奖学金
    2026-2027学年，北京大学；集成电路学院授予10人
  • March 2026
    ASPLOS 2026 Best Paper Award
    "Finding Reusable Instructions via E-Graph Anti-Unification" (ISAMORE), recognized with ASPLOS 2026 Best Paper Award (5/1048)
  • 2018-2019
    Yang Fuqing & Wang Yangyuan Academician Scholarship
    Awarded to only 5 students at EECS, Peking University, for academic excellence
  • 2019-2020
    Shenzhen Stock Exchange Scholarship
    Awarded to 17 students from EECS, Peking University
  • 2018-2020
    Merit Student
    Awarded to top 10% students for comprehensive excellence
  • August 2020
    Second Place in EDAthon 2020
    IEEE CEDA Hong Kong Chapter - Programming Competition on Electronic Design Automation
  • July 2017
    Second Prize in NOI 2017
    National Olympiad in Informatics, China Computer Federation
  • May 2017
    Second Prize in APIO 2017
    Asia Pacific Informatics Olympiad (China District), China Computer Federation

Tutorials

  • January 2026
    APS: An MLIR-Based Hardware-Software Co-design Framework
    ASP-DAC 2026, Hong Kong, China
  • May 2025
    Agile Hardware Specialization: A toolbox for Agile Chip Front-end Design
    ISEDA 2025, Hong Kong, China
  • March 2025
    Agile Hardware Specialization (AHS): A toolbox for Agile Chip Front-end Design
    ASPLOS 2025, Rotterdam, Netherlands
  • March 2025
    Agile Hardware Specialization: A toolbox for Agile Chip Front-end Design
    DATE 2025, Lyon, France
  • January 2025
    AHS: An EDA toolbox for Agile Chip Front-end Design
    ASP-DAC 2025, Tokyo, Japan

Teaching Experience

  • Spring 2022 & Fall 2022
    Teaching Assistant - High-level Chip Design
    Peking University
  • Fall 2020
    Teaching Assistant - Introduction to Computer Systems
    Peking University