Youwei Xiao

self_at_fuzhou.jpg

Youwei Xiao 肖有为

School of Integrated Circuits

Peking University

Beijing, China

I am a Ph.D. candidate at the School of Integrated Circuits, Peking University, advised by Prof. Yun Liang, and a Large Language Model Algorithm Intern at ByteDance Seed. My current research centers on agents for LLM infrastructure on emerging AI chips. I contribute to native multi-agent coding systems, focusing on multi-agent orchestration strategies and workflow customization through programmable concurrency and human-in-the-loop workflows for long-horizon systems development.

I apply these approaches to LLM infrastructure on emerging AI chips. I evolve an abstraction-layered operator-optimization skill system and an agent-native compiler stack for operator implementation, chip-architecture-aware performance optimization, and automated toolchain development. This work improves model-serving efficiency on new chips, while real development data and trajectories become training signals for model-capability improvement.

My earlier research follows a compiler-driven approach to agile chip design: use DSLs and multi-level IRs to expose architecture choices, then build compilation and synthesis stacks that optimize software and hardware together. Hector provides multi-level IRs for hardware synthesis. Cement couples the cycle-deterministic CmtHDL DSL with the CmtC compiler for timing analysis and control synthesis. APS/Aquas builds an MLIR-based stack from architecture DSLs to hardware synthesis and software compilation, then extends it with domain-specific memory/synthesis directives and an e-graph retargetable compiler.

Across this compiler-driven stack, ISAMORE (ASPLOS 2026 Best Paper) and EggMind structure optimization search with formal and LLM-guided methods; Clay, Cayman, and SkyEgg automate microarchitecture and accelerator optimization; and IntelliC makes compiler artifacts inspectable for human-agent collaboration. PTO Runtime carries compiled task graphs onto Ascend chips and LingQu SuperPods, while Hive and Spine extend the story toward multi-agent LLM infrastructure and cross-layer agentic co-design. These systems are now the technical substrate on which my native multi-agent work operates.

news

May 28, 2026 Awarded 博士研究生校长奖学金 for the 2026-2027 academic year, with 10 recipients selected from the School of Integrated Circuits.
May 09, 2026 Awarded 学术之芯, a 2026 academic honor from Peking University’s School of Integrated Circuits granted to 8 recipients.
Mar 31, 2026 ISAMORE wins the ASPLOS 2026 Best Paper Award (5/1048)!

selected publications

  1. Preprint
    LLM-Guided Strategy Synthesis for Scalable Equality Saturation
    Chenyun Yin*Youwei Xiao*, Yuze Luo, and 2 more authors
    2026
  2. Preprint
    Hive: A Multi-Agent Infrastructure for Algorithm- and Task-Level Scaling
    Zizhang Luo, Yuhao Luo, Youwei Xiao, and 3 more authors
    2026
  3. Arch 2.0
    EggMind: LLM-Driven Two-Dimensional Intelligence for Scalable Equality Saturation
    Youwei Xiao, Chenyun Yin, and Yun Liang
    In Architecture 2.0: Workshop on AI for Computing Systems Design, 2026
  4. ASPLOS
    Finding Reusable Instructions via E-Graph Anti-Unification
    Youwei Xiao, Chenyun Yin, Yitian Sun, and 2 more authors
    In Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2 (ASPLOS ’26), 2026
    Best Paper Award at ASPLOS 2026 (5/1048 submissions).
  5. Preprint
    Aquas: Enhancing Domain Specialization through Holistic Hardware-Software Co-Optimization based on MLIR
    Yuyang Zou, Youwei Xiao, Yansong Xu, and 6 more authors
    2025
  6. Preprint
    SkyEgg: Joint Implementation Selection and Scheduling for Hardware Synthesis using E-graphs
    Youwei Xiao, Yuyang Zou, and Yun Liang
    2025
  7. Preprint
    Cement2: Temporal Hardware Transactions for High-Level and Efficient FPGA Programming
    Youwei Xiao, Zizhang Luo, Weijie Peng, and 2 more authors
    2025
  8. ICCAD
    Invited Paper: APS: Open-Source Hardware-Software Co-Design Framework for Agile Processor Specialization
    Youwei Xiao, Yuyang Zou, Yansong Xu, and 6 more authors
    In Proceedings of the 44rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’25), 2025
  9. ICCAD
    Clay: High-level ASIP Framework for Flexible Microarchitecture-Aware Instruction Customization
    Weijie Peng*Youwei Xiao*, Yuyang Zou, and 2 more authors
    In Proceedings of the 44rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’25), 2025
  10. DAC
    Cayman: Custom Accelerator Generation with Control Flow and Data Access Optimization
    Youwei Xiao, Fan Cui, Zizhang Luo, and 2 more authors
    In Proceedings of the 62nd ACM/IEEE Design Automation Conference (DAC ’25), 2025
  11. LATTE
    cmt2: Rule-Based Hardware Description in Rust with Temporal Semantics
    Youwei Xiao, Zizhang Luo, and Yun Liang
    In 5th Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE’25), 2025
  12. FPGA
    An Empirical Comparison of LLM-based Hardware Design and High-level Synthesis
    Fan Cui, Youwei Xiao, Kexing Zhou, and 1 more author
    In Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’25), 2025
  13. FPGA
    Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis
    Youwei Xiao, Zizhang Luo, Kexing Zhou, and 1 more author
    In Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’24), 2024
  14. ICCAD
    HECTOR: A Multi-Level Intermediate Representation for Hardware Synthesis Methodologies
    Ruifan Xu, Youwei Xiao, Jin Luo, and 1 more author
    In Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’22), 2022